Additional enhancements in this release include:

• High-speed routing improvements: controls for matched length nets and differential routing improvements.
• Square and chamfered corners, DXF-in import, and via matrixing enhancements for RF design.
• Blind/buried via drill table improvements: designs with partial vias (blind or buried) are automatically updated with the layer pairs and drill count of the partial vias in the design.
• Alpha-numeric pin improvements: simplifies creation of large BGA-based parts.
• ECO enhancements: includes comparison of design rules between the schematic and layout databases.
• Design for fabrication (DFF) analysis: powerful fabrication checks, such as acid trap, starved thermals, solder mask slivers are checked in the CAD environment and database, allowing the designer to identify and correct manufacturing problems in PADS Layout, before Gerber generation.
• Pin number visibility: the user has the ability to turn on/off the visibility of the component pin numbers, either numeric or alpha-numeric, improving designer productivity during routing.
• SI analysis: integration of DxDesigner and the HyperLynx LineSim tool through a new interface allows fast transfer of a circuit for analysis and back annotation of termination resistor values.
• Analog simulation: provides a board level simulation analysis and verification through a common schematic editor for both simulation and PCB design entry.